1. Technical Field
The invention relates to a chip structure and a multi-chip stack package. Particularly, the invention relates to a chip structure with vertical electrical conduction and a multi-chip stack package.
2. Related Art
In today's information society, users pursue high-speed, high-quality and multi-functional electronic products. In view of an appearance of the electronic product, the design of the electronic product tends toward lightness, thinness, shortness and smallness. In order to achieve the aforementioned object, many companies introduce a systematic concept into circuit design, such that a single chip may have multiple functions to decrease the number of the chips configured in the electronic products. Moreover, regarding an electronic packaging technique, to cope with the design trend of lightness, slimness, shortness and smallness, a multi-chip module (MCM) package, a chip scale package (CSP) and a stacked multi-chip package, etc. are developed. Moreover, a three-dimensional integrated circuit (3D IC) integration technique becomes a trend of today's electronic packaging technique.
In detail, the 3D IC integration technique is one of the most effective structures capable of improving performance of the electronic products, which allows a vertical stacking connection of multiple chips to integrate more computing power, memories and other functions into an extremely tiny device. However, the conventional 3D IC integration of through silicon via (TSV) requires manufacturing processes of laser perforation, physical vapor deposition (PVD), and plasma-enhanced chemical vapor deposition (PECVD), etc. Therefore, the manufacturing cost of the TSV is very high due to expansive vacuum and dry processing equipment and consumptive materials thereof. Therefore, it is urgent and necessary to reduce the high cost of the 3D IC integration.